Field of the Invention
The present invention relates to integrated circuit fabrication, and more particularly to methods of fabricating high-density integrated circuit devices.
Description of Related Art
Photolithographic processes can be used to form various types of integrated circuit structures on a semiconductor wafer. In photolithography, features of these structures are typically created by exposing a mask pattern (or reticle) to project an image onto a wafer that is coated with light sensitive material such as photo resist. After exposure, the pattern formed in the photo resist may then be transferred to an underlying layer (e.g. metal, polysilicon, etc.) through etching to create the desired features.
One problem associated with manufacturing devices having very small features arises because of the line width variation (or Critical Dimension, CD) introduced by the photolithographic processes. Specifically, resist material properties, process conditions and other factors can cause random variations in the width and spacings of a patterned line of resist over its length. The variation along just one edge is called line edge roughness (LER).
In a typical lithographic patterning process, a series of parallel lines of resist are used as an etch mask to create a corresponding series of parallel lines of material in the underlying layer. In such a case, random variations in the patterned parallel lines of resist will be transferred to the critical dimensions of the parallel lines in the underlying layer. As process technologies continue to shrink, this random variation becomes a greater percentage of the critical dimension of the parallel lines of material, which can result in significant performance variability in devices such as transistors implemented utilizing these lines of material.
In addition, such a process will result in random, uneven variations in the spacing between the adjacent parallel lines of resist, which in turn is transferred to the spacing between the adjacent lines of material. This uneven spacing introduces variations in the thermal stress induced on either side of a given line of material during manufacturing, which can result in reliability issues and reduce yield. For example, a typical fabrication technique includes forming shallow trench isolation (STI) structures of insulator material between lines of silicon. During the manufacturing process, these structures undergo thermal cycling which introduces thermo-mechanical stresses between the silicon and the adjacent STIs. The difference in spacing on either side of a given line of material results in variations in the induced thermal stresses on either side, which can significantly deform and possibly cause the silicon to fall over during manufacturing.
Accordingly, it is desirable to provide high-density integrated circuit devices which overcome or alleviate issues caused by critical dimension variations introduced by photolithographic processes, thereby improving performance and manufacturing yield of such devices.